AINT: README

Source code for AINT is available at the URL:

http://esl.cs.colorado.edu/Aint/AINT.tar.gz

This distribution contains the aint source code, example simulators, and several simple tests programs. The source-code alone can be downloaded by retrieving the file

http://esl.cs.colorado.edu/Aint/aint_src.tar.gz

New Features

1. PAGED ADDRESS SPACE

   The entire simulated address space is now implemented using page tables. Only memory locations read/written by the application are explicitly allocated. This results in significant reductions in memory used by AINT.

   This change is transparent to the back-end simulator

2. EVENT SPECIFICATION

   It is now possible to specify the events that cause the back-end simulator functions to be called. In particular, the user can specify (using command line options) flagging of all memory references, only shared references, only private references, or every instruction.

3. SIM_INST()

   The back-end function sim_inst is called after every instruction (other than read, write, ld_l, st_c and mb insts), if instruction tracing is specified.

   The *ptask->pevent structure passed to sim_read, sim_write, sim_load_locked, sim_store_conditional, sim_memory_barrier and sim_inst functions contains a field (struct icode *picode), that points to the internal structure representing the current instruction. The icode structure is defined in $AINTDIR/include/icode.h.

4. SIM_USER(): CALL-BACK MECHANISM

   The back-end function sim_user is provided as a call-back mechanism from the application into the back-end simulator. To use this feature, applications need to declare and call an empty function called sim_user, defined in sim.h. AINT remaps the call to the actual back-end function sim_user().

   Whenever the application calles sim_user, control is transfered to the simulator's sim_user function with the same argument (values) as the application-space sim_user. This can be used to trap special macro-events such as lock acquires and releases.

5. SPLASH2: QUEUEING LOCKS

   The Splash2 implementation provided with AINT now uses queueing locks to reduce contention (on a real multiprocessor). The queueing locks implementation (ulocks.c) also uses the sim_user CALL-BACK mechanism discussed above.

6. AINT NOW RUNS MULTIPROCESSOR SPLASH2 PROGRAMS CORRECTLY

   Several bugs in the Splash2 implementation have been fixed, and these programs can now be run with several processors (we have tested up to 16) on AINT as well as natively.

Features added in the previous release

1. The event structure, available to the back-end through the ptask->pevent pointer, contains the new fields:

     int size;    /* size in bytes of the  data for read/write */
     long data;     /* data value for read/write */
   

   The size specifies whether the load/store involves a longword (4 bytes) or a quadword (8 bytes). The data field contains the contents of the memory location to be loaded into a register (load instruction), or the value to be written to memory (store instruction).
2. In sim_read(), ptask->pevent->data contains valid data only if the address translation produces a meaningful physical (aint-space) address. If the translated address for a read or write is not valid, the ptask->pevent->paddr field is null, and the back-end is expected to translate ptask->pevent->vaddr, and return valid data in ptask->pevent->data which aint will write to a register.
3. In sim_write(), the pevent->data contains the value to be written to memory. If paddr is invalid, the back-end is expected to process the write. This can be done in two ways:
   • The back-end translates ptask->pevent->vaddr to its own address space, and returns a valid pointer in ptask->pevent->paddr, to which AINT will commit the write.
   • The application processes the vaddr, and AINT needs to do no more. In this case, the back-end should set the paddr to NULL (0).
4. Even if the paddr is valid, the back-end may override the store operation by changing ptask->pevent->data (which will be written to *paddr), or by returning a null value in paddr, which will indicate an empty (no-op) commit operation.

Please direct questions about AINT to Vega Paithankar (pvega@cs.colorado.edu)